Semiconductor Startup Claims it Can Cut Chip Power Consumption in Half

As electronic devices become smaller and offer an ever-widening array of features, controlling their power consumption becomes a key hurdle. Los Gatos, California-based startup semiconductor company SuVolta claims it has come up with a new solution: its SuVolta's PowerShrink low-power CMOS (complementary metal–oxide–semiconductor) platform, which the company says significantly lowers power consumption without sacrificing performance across a wide range of integrated circuit (IC) products, including the processors, SRAMs (static random-access memory) and SOCs (system-on-a-chip) that are critical to today's mobile systems.

By enabling continued voltage scaling as well as leakage reduction, the SuVolta technology can cut in half the active power consumption of 65nm process technologies as well as reduce leakage power consumption by five times or more, says the company.

“SuVolta's DDC sub-micron technology addresses threshold voltage control by limiting random and other sources of dopant fluctuation while simultaneously improving carrier mobility and reducing device capacitance so as to maintain circuit speed at lower power,” said SuVolta CTO Scott Thompson.

Compatible with current manufacturing and design infrastructure, SuVolta's new platform, which is driven by its proprietary Deeply Depleted Channel CMOS transistor, leverages existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials. SuVolta’s PowerShrink platform also uses conventional design tools and design flows.

According to the company, the technology has been demonstrated on SRAM blocks operating below 0.5V. “This sub-0.5V operating voltage is among the lowest reported for 65nm CMOS technology, and is lower than typical SRAM minimum operating voltage of 0.8V and higher,” noted the company.

Fujitsu (News - Alert) is reportedly the first company to license SuVolta's technology.

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